As designers strive to improve the capabilities of new ICs, minimization of IC size continues to be an underlying goal. Typically, IC designs utilize previously developed circuit designs, from a library of circuit designs in new combinations and configurations to create wholly new designs capable of performing new functions or perhaps optimizing the performance of the previous IC designs. While some individual IC designs have been optimized in terms of performance and size, the combination of these circuits with other circuits into new custom designed ICs often utilize a re-configuration of transistor geometry to provide the optimal design of the overall new custom designed IC.
When custom designing a new high performance IC, individual transistors may be tuned to provide optimal speed. However, manually tuning individual transistor is both tedious and error-prone. While some automated transistor sizing tools exist to optimize individual transistors, the individual transistors still benefit from an optimal physical layout design to provide an optimal IC. Conventional layout designs place individual transistors on a layout using a row-based design style. In most cases, conventional row-based layout designs result in an inefficient utilization of chip area because the individual transistors are of non-uniform size and shape.
Transistor folding is a method of re-configuring the geometry of a known transistor design in order to minimize total chip area, while retaining the performance characteristics of the known design. In custom IC physical layout design, high performance requirements of new circuit designs nay necessitate the integration of various transistor devices of different sizes. In the typical row-based layout design style, non-uniform transistor heights in a row tend to waste overall IC chip area. Therefore, it is highly desirable to provide a system and method of transistor device folding which takes advantage of the different rows' lengths to achieve efficient area utilization of the entire IC layout.